此题为判断题(对,错)。
第1题:
有SQL语句: SELECTDISTINCT系号FROM教师WHERE工资>=; ALL(SELECT工资FROM教师WHERE系号="02") 与如上语句等价的SQL语句是
A.SELECTDISTINCT系号FROM教师WHERE工资>=; (SELECTMAX(工资)FROM教师WHERE系号="02")
B.SELECTDISTINCT系号FROM教师WHERE工资>=; (SELECTMIN(工资)FROM教师WHERE系号="02")
C.ELECTDISTINCT系号FROM教师WHERE工资>=; ANY(SELECT工资FROM教师WHERE系号="02")
D.SELECTDISTINCT系号FROM教师WHERE工资>=; SOME(SELECT工资FROM教师WHERE系号="02")
第2题:
有SQL语句:SELECT DISTINCT系号FROM教师WHERE 工资>=ALL (SELECT 工资FROM教师WHERE系号=\"02\") 与如上语句等价的SQL语句是
A.SELECT DISTINCT系号FROM教师WHERE工资>=(SELECT MAX(工资)FROM教师WHERE 系号="02")
B.SELECT DISTINCT系号FROM教师WHERE工资>=(SELECT MIN(工资)FROM教师WHERE 系号="02")
C.SELECT DISTINCT系号FROM教师WHERE工资>=(ANY(SELECT(工资)FROM教师WHERE 系号="02")
D.SELECT DISTINCT系号FROM教师WHERE工资>=(SOME (SELECT(工资)FROM教师WHERE 系号="02")
第3题:
下列Moore型状态机采用Verilog语言主控时序部分正确的是:
A.always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end
B.always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end
C.always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state;
D.always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
第4题:
有SQL语句: SELECT DISTINCT 系号 FROM 教师 WHERE 工资>=; ALL(SELECT 工资 FROM 教师 WHERE 系号 =“02”) 与如上语句等价的SQL语句是
A.SELECT DISTINCT 系号 PROM 教师 WHERE 工资>=; (SELECT MAX(工资)FROM 教师 WHERE 系号=“02”)
B.SELECT DISTINCT 系号 FROM 教师 WHERE 工资=; (SELECT MIN(工资)FROM 教师 WHERE 系号=“02”)
C.SELECT DISTINCT 系号 FROM 教师 WHERE 工资>=; ANY(SELECT 工资 FROM 教师 WHERE 系号=“02”)
D.SELECT DISTINCT 系号 FROM 教师 WHERE 工资>=; SOME(SELECT 工资 FROM 教师 WHERE 系号=“02”)
第5题:
定义状态机当前状态为state ,次态为next _state; 输入a,输出b, 则下列为Mealy状态机的写法是:
A.always@(posedge clk) case (state ) 0:next_state<=1; 1:next_state<=x;#B.always@(posedge clk) case (state ) 0: if(a==0)next_state<=1; else next_state<=x; 1:next_state<=x;#C.always@(posedge clk) case (state ) 0: if(state==0)next_state<=1; else next_state<=x; 1:next_state<=x;#D.以上都不对第6题:
定义状态机当前状态为state ,次态为next _state; 输入a,输出b, 则下列为Mealy状态机的写法是:
A.always@(posedge clk) case (state ) 0:next_state<=1; 1:next_state<=x;#B.always@(posedge clk) case (state ) 0: if(a==0)next_state<=1; else next_state<=x; 1:next_state<=x;#C.always@(posedge clk) case (state ) 0: if(state==0)next_state<=1; else next_state<=x; 1:next_state<=x;#D.以上都正确